1. Field of the Invention
The present invention relates to a layer build-up method for manufacturing a multi-layer board. More particularly, the present invention relates to a layer build-up method for manufacturing a multi-layer board such that different layers are connected by solid interconnects.
2. Description of the Related Art
Due to ever-increasing consumer demands for higher functionality, lighter weight, and smaller size of electronic products, most electronic products are designed in this direction. The outcome of this trend is a continuous increase in the level of integration of the integrated circuits. To decrease the volume of a chip package, the number of layers in a chip-mounting substrate board has to increase. A multi-layer substrate board is indispensable, especially for a package having a highly integrated chip or a multi-chip module with several chips inside.
The different layers on a multi-layer substrate board must somehow be connected. Conventionally, different layers are connected by forming plated through holes (PTH). The plated through holes are formed by drilling a set of through holes in the substrate board, and chemically or electrically coating the holes with a metallic layer chemically or electrically. However, drilling holes in the multi-layer board to form the plated through holes often destroys the integrity of the voltage layer, leading to capacitance loss and an increase in electrical noise. In addition, the holes occupy a large portion of the usable area and hinder wiring layout. Therefore, industry has gradually adopted a layer build-up method for forming a multi-layer board. The board is formed by sequential lamination using blind vias to connect neighboring layers. A blind via is formed by drilling a hole through one layer to its adjacent layer, only. A layer of copper is plated, and finally filler material or conductive material such as copper or silver paste is used to fill the hole. Using blind vias to connect sequentially laminated layersgreatly reduces area needed for interconnects and the voltage layer within the multi-layer board can have better integrity.
Although sequential lamination is able to reduce area occupation of interconnects, adjacent wiring layers are actually connected through a thin coat of copper lining the blind via. Thus, inter-layer impedance is increased and the overall electrical properties of the multi-layer board may be affected. Furthermore, conventional sequential lamination processes for forming a multi-layer board rely on attaching a copper foil to the board before drilling a hole. However, the filler material has minimal resistance against laser drilling, mechanical drilling or etching operation, and thus cannot serve as a stopping layer. Therefore, the vias in each layer must be alternately distributed just to prevent holes from drilling into an underlying wiring layer. If filler materials such as copper or silver paste are used inside the blind vias, electrical conductivity between layers may improve. However, both copper paste and silver paste are expensive materials. In addition, the paste may not fill the blind vias entirely, and electrical conductivity may not improve that much.
FIGS. 1A through 1C are schematic cross-sectional views showing the progression of manufacturing steps for producing a multi-layer board using a layer build-up process developed by Toshiba. The method is called a buried bump interconnect technology (BBIT). As shown in FIG. 1A, solid conical bumps 12 are formed on a copper foiled substrate 10 in places wherein contact circuits 16 are desired. The solid conical bumps 12 on the substrate 10 are formed by smearing silver paste on a metallic mold plate and pressing on the substrate 10. External profile, height and hardness of each bump must be meticulously controlled. The copper-foiled substrate 10, a non-knitted dielectric layer 14 and core substrate 19 having an inner dielectric layer 18 and an outer conductive layer 16 are pressed together to form a structure shown in FIG. 1B. Because the conical bumps 12 are relatively hard, the pointed edge of each bump 12 is able to pierce through the dielectric layer 14 and contact a circuit line 16. When the conical bumps 12 pierce through the dielectric layer 14 and hit upon the conductive layer 16, the conical bumps 12 are forged into bowl bumps 12xe2x80x2. In the last stage, the copper-foiled substrate 10 is patterned to form a conductive layer as shown in FIG. 1C. The entire process can be repeated several times to obtain a multi-layer board.
Since solid bumps instead of hollow blind vias are formed inside the aforementioned multi-layer board, electrical characteristics of the board are improved. However, hardness and external profile of each conical bump 12 has to be carefully controlled in order to have proper contact with the conductive layer 16. Moreover, the metallic mold plate and the silver paste are expensive, and costly equipment has to be used in the process.
Accordingly, one object of the present invention is to provide a layer build-up process for forming a multi-layer board that uses fewer steps and less expensive equipment.
A second object of the invention is to provide a layer build-up process for forming a multi-layer board capable of having a plurality of solid interconnects all stacked upon each other. Consequently, circuit paths are shorter and reactance is smaller. In addition, wiring area can be smaller.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a layer build-up process for forming a multi-layer board. A conductive substrate is provided. Bumps are formed on the conductive substrate by half-etching. A dielectric layer is formed, filling the space between the bumps. The dielectric layer can be formed by drilling a series of holes that correspond in position to the bumps on a plastic (pre-preg) plate, and then pressing together the plastic plate and the conductive substrate. Alternatively, the dielectric layer can be formed by screen-printing, dispensing, or coating a photosensitive polymer followed by a photolithographic process.
Another half-etching operation is carried out to remove a portion of the bumps so that the top surface of each bump is at a level lower than the top surface of the dielectric layer. A layer of conductive plastic or solder paste is smeared on top of the bumps. The conductive substrate with the dielectric layer and a core substrate are stacked together. The core substrate has a multi-layer structure that includes a plurality of alternately placed insulation layers and wiring layers. When the conductive substrate with the dielectric layer and the core substrate are pressed together, bumps on the conductive substrate touch corresponding contact points on wiring layer. Hence, the conductive substrate and the wiring layer are electrically connected. Heat is next applied to make the dielectric material fluidic so that the space between the conductive substrate and the wiring layer is filled. After cooling, the conductive substrate and the wiring layer are interlocked together by the solidified dielectric material. Using photolithographic and etching processes, the conductive substrate is patterned to form a second wiring layer. The second wiring layer, the bumps and the dielectric layer together constitute a composite layer. The aforementioned steps can be repeated to form a multi-layer board that includes a stack of these composite layers over a core substrate.
The layer build-up process of this invention uses solid bumps as interconnects between different wiring layers. Hence, no filler material is required to fill interconnects and the fabricated multi-level board has better electrical properties. In addition, the bumps in the dielectric layer can stack on top of each other. Without the alternation of layers, wiring area is reduced and circuit paths are shortened. Consequently, circuit reactance is lowered. Furthermore, by using an etching method to form the bumps, processing steps are simpler, control is easier and equipment cost is lower.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.